Non-volatile memories, such as flash memories, for example, carry out erase operations with the application of high biasing voltages on the bulk of the substrate in which the memory array is integrated. In particular, this may be done for implementing the Fowler-Nordheim tunnel effect.
In the case of page-mode flash memories, the erase operations may further be carried out by page, i.e., involving all the memory cells of a same row of the array. Reference will be made in what follows to this case, without implying any loss of generality.
FIG. 1 shows, by way of example, the transistor structure of a memory cell 1 belonging to a memory array of a non-volatile memory device of a flash type (not illustrated). The memory cell 1 is provided in a substrate 2 of semiconductor material, for example, with N-type doping. The substrate 2 has a top surface 2a, a well 3, in the example P-type doping is provided in the substrate 2, defining the bulk (B) of the memory cell 1.
The memory cell 1 comprises a source region (S) 4 and a drain region (D) 5, which define the current-conduction terminals of the transistor, and which are both provided within the well 3, with opposite doping. In the example, N-type doping is provided for the well. A floating-gate region (FG) 6 is set above the top surface 2a of the substrate 2 and is separated from the latter by a tunnel-oxide region 7. A control-gate region (CG) 8 defines the control terminal CG of the transistor and is set above the floating-gate region 6 and is separated from the latter by a gate-oxide region 9.
During operation, data stored in the memory cell 1 is a function of an electrical charge QFG stored in the floating-gate region 6. Erasing the memory cell 1 requires removal of the electrical charge QFG by extraction of electrons from the same floating-gate region 6.
The above extraction of electrons is obtained by applying a high electrical field between a bulk terminal B of the memory cell 1 connected to the well 3, and a control-gate terminal CG of the memory cell 1 connected to the control-gate region 8. This is to activate the Fowler-Nordheim tunnel effect through the tunnel-oxide region 7 and to determine migration of the electrons through the same tunnel-oxide region 7.
In particular, the high electrical field required for the erase operation is generated by applying a high potential difference between the control-gate terminal CG and the bulk terminal B.
In one implementation, the control-gate terminal CG has a control voltage VCG set at a negative high-voltage value −HV, for example, −10 V. The bulk terminal B has a bulk voltage VB set at a positive high-voltage value +HV, for example, +10 V.
In a known way, not described in detail herein, the biasing voltages are generated by an appropriate decoding circuitry, including MOSFETs, coupled to the memory array.
As illustrated in FIG. 2a (which shows the plot of the drain-to-source current IDS versus the gate-to-source voltage VGS of the memory cell 1), following the erase operation, the electrical charge QFG stored in the floating-gate region 6 undergoes a reduction. The electrical charge QFG, passes from a first (negative) value QFG′ (with the memory cell 1 in the programmed state) to a second value, in the example zero or positive, QFG″, indicating the erased state of the memory cell 1. Following the erase operation, a corresponding reduction of the threshold voltage (generally designated by Vth) occurs.
Operation of the memory cell 1 described above may lead to a considerable degree of stress in the memory cells that share the same bulk as the memory cell 1, given the high biasing voltage of the bulk terminal B.
Furthermore, even if the transistors in the memory device (for example, the MOSFETs in the decoding circuitry) have high-voltage characteristics (for example, they have suitable thicknesses of the gate oxides and suitable geometrical dimensions), they are able to withstand, without undergoing damage or failure, a maximum voltage between their own gate, source, and drain terminals. In flash-memory devices, this maximum value of voltage is, for example, 10 V (i.e., equal to the high-voltage value HV).
When a memory cell 1 is selected for erasing (by bringing the control voltage VCG to the negative high-voltage value −HV, −10 V in the example, and the bulk voltage VB to the positive high-voltage value +HV, +10 V in the example), the control-gate terminal of the other memory cells 1 that have not been selected may not be driven by the same decoding circuitry (and by the same MOSFETs) to a voltage higher than 0 V. This is done to not generate voltage differences between the terminals of the transistors that are higher than the high voltage HV (which represents the maximum voltage that may be withstood).
Consequently, in the non-selected memory cells 1 an undesirable phenomenon of loss of charge, the so-called soft erase, occurs on account of the high voltage. In the example this is +10 V, present between the control-gate terminals (set, for example, at 0 V) and the bulk terminals (set, for example, at +10 V).
As illustrated in FIG. 2b, the erase operation thus entails a reduction of the electrical charge QFG stored in the floating-gate region 6 also of the non-selected memory cells 1, as represented by a dashed line, to a value QFG between the first value QFG′ and the second value QFG″.
The programmed memory cells thus require, to prevent any losses of the data stored, periodic refresh operations, with a refresh frequency that depends on the number of erase cycles carried out on the other rows, during which the same memory cells 1 have remained non-selected.
The soft-erase stress acting on the non-selected memory cells 1 may be quantified by applying the following expression:Stress=N·R·Ter 
where N is the number of erase cycles, R is the number of rows involved in the erase cycles, and Ter is the duration of the erase pulse.
To reduce this stress, which is defined in general as bulk stress, known non-volatile-memory devices use division of the memory array into a number of sectors (i.e., sectoring), each of which has an insulated bulk well. In the example illustrated previously, the insulated bulk wells have a P-type doping. In this way, in each sector, the stress that occurs during erase affects only the memory cells associated to the rows Rsec belonging to the sector itself (with Rsec<R).
FIG. 3 shows a known non-volatile memory device 10, for example, of a flash type, divided into a plurality of sectors 12 physically distinct and electrically insulated from one another. Each sector 12 comprises a bulk well 14, provided within the substrate 2 of an N-type and having an opposite type of doping (in the example, a doping of a P-type). The various bulk wells 14 are insulated from one another. As an alternative, bulk wells 14 may be provided within a well of opposite doping, of an N-type, buried in the substrate 2.
Each sector 12 further comprises a respective plurality of rows of memory cells 1 (represented schematically) with the source and drain regions (not illustrated) provided within the respective bulk well 14, and arranged in rows (wordlines, WL) and columns (bitlines, BL). There is also a respective local control-gate decoder 16.
In particular, the control-gate terminals CG of the memory cells 1 of a same row are biased at a same control-gate voltage VCG, and the local control-gate decoder 16 is configured to appropriately select and bias the control-gate terminals CG of the various rows of memory cells 1 at respective values of control voltage VCG. This is to enable implementation of the programming, reading, and erase operations in the memory array.
The local control-gate decoders 16 are distinct and separate from one another, and are provided in the respective sector 12 of the memory array. Each sector 12 further comprises a respective local bitline decoder 18 configured to select and appropriately bias local bitlines BL, to which the drain terminals of the memory cells 1 of a same column are connected.
The local bitline decoder 18 comprises suitable selection transistors 19 (illustrated schematically in FIG. 3), which are controlled by selection signals, designated as a whole by SL. The selection signals are supplied by a controller of the non-volatile memory device 10, and are designed to couple the local bitlines BL to global bitlines of the memory array (the main bitlines), designated by MBL, that are in common for the various sectors 12.
This sectoring of the memory array, which, as has been pointed out, enables reduction of the stress in the memory cells 1 due to the erase operations, has, however, some disadvantages.
In particular, sectoring entails a considerable increase of the occupation area of the non-volatile memory device 10 on account of the need to separate from one another the various bulk wells 14, and further to provide in a distinct and separate manner the corresponding circuitries for row decoding and biasing and for column decoding and biasing.
It is thus required to reach a compromise between the number of sectors 12, and thus the number of rows associated to each sector 12, and the desired reduction of bulk stress. For example, known devices for a 1-MB memory using eight 128-KB sectors (or four 256-KB sectors), with a number of rows per sector equal to 512.
It is evident that, as the number of rows in each sector 12 increases (to prevent an excessive increase of area), the residual bulk stress due to the erase operations, which concerns all the non-selected rows within the sector 12, increases when a selected row is subjected to erase.
It is thus necessary to plan operations of refreshing of the rows of memory cells 1 following the erase operations, with a consequential increase in the times associated to the erase operations themselves.
Furthermore, a counter is to be provided for each sector 12 to monitor and keep under control the number of erase cycles and the number of refresh operations on the memory cells 1.
Non-volatile memory devices of a known type are not altogether satisfactory, for example, in regards to management of the erase operations and of the associated stresses in the memory cells, and in general, in the transistors of the same memory devices. There is a need to provide an improved approach for a non-volatile memory device, which will enable the problems highlighted above to be addressed.